The present invention is directed to fabrication of electronics, optoelectronics, and microelectromechanical systems (MEMS) devices. The method is particularly applicable to fabrication of double-sided devices, i.e. the devices which functionalities require designs and manufacturing processes on both front and back sides of the substrates.
A good example of double-sided devices is crystalline silicon solar cells. In a crystalline silicon solar cell, different materials and structures are fabricated at front and back sides of a silicon substrate. Upon a solar illumination on the cell, positive/negative charges are generated in the silicon substrate and electrical currents are carried out by metal contacts fabricated on the surfaces.
The category of double-sided devices also include several types of semiconductor power devices, including power metal oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT). Power MOSFET is the most widely used low-voltage (<200 V) switch. It can be found in power supplies, DC to DC converters and low voltage motor controllers. IGBT combines the simple gate-drive characteristics of MOSFETs with the high-current and low-saturation-voltage capability of bipolar transistors in a single device. It is used in medium- to high-power applications ranging from power inverters in renewable energy industries to electric vehicles/trains and energy efficient appliances. Both power MOSFET and IGBT are three-terminal semiconductor devices. An isolated gate FET structure and two terminals are fabricated on one side of the silicon wafer, with the third terminal at the other side of the substrate.
Some microelectromechanical systems (MEMS) devices are also both sided. Sensors/actuators and other structures are often constructed with patterning and processing on both sides of a silicon wafer, and can be integrated with microprocessors fabricated on the same substrate.
The manufacturing process of double-sided devices can be more complicated than that of single-sided devices, which have designs on only one side of the substrates. Some of the challenges in double-sided device fabrication are associated with a cross contamination between two sides of the substrates from double-sided manufacturing processes. Many manufacturing processes are double-sided in nature, i.e. the processes that proceed on both sides of the substrates at the same time. Such double-sided process step(s) can include but not limited to cleaning, film deposition, diffusion, etch, ion implantation, and patterning. However, double-sided devices generally require different designs and process steps on the front and back sides of the substrates. As a result, some double-sided manufacturing processes can be desirable or necessary for one side of substrate in double-sided devices, but may not be desirable or must be avoided on the other side of the substrate. FIG. 1 illustrates a generic manufacturing flow of double-sided devices. Manufacturing processes required for one side of the substrate are first carried out. Some of the manufacturing processes are double-sided and contaminate the other side of the substrate. As a result, the other side of the substrate needs to be cleaned or polished prior to the subsequent manufacturing processes on the other side of the substrate.
Such cleaning/polishing processes can be tedious and costly. Under some circumstances (e.g. crystalline silicon solar cell fabrications), the cleaning/polishing processes are avoided in alternative manufacturing flows, albeit with compromises in device performances. FIG. 2 illustrates a baseline manufacturing flow of crystalline silicon solar cells. A silicon substrate 1 first passes through wet etch steps to remove contamination and damaged silicon on the surface and to undergo surface texturing 2. The next manufacturing process is emitter formation. With a regular boron doped (p-type) silicon substrate, an n-type emitter region is formed, typically by a high temperature (800-900 C) phosphorus oxychloride (POCl3) diffusion process 3 carried out in a furnace. A phosphosilicate glass (PSG) layer is also formed during the POCl3 diffusion process. It is removed in a subsequent HF-based wet etch 4. The next step in the process flow is an edge isolation step 5 to remove phosphorus dopant from the edges of the substrates. The wafer front surface is then coated by an anti-reflective (AR) layer, e.g. a hydrogenated silicon nitride (SiNx:H) layer 6. Finally, in steps 7 and 9, front-side metal contacts (Ag) and back-side metals (Al/Ag) are fabricated by screen printing and then solidified through a final co-firing process.
A number of manufacturing steps shown in FIG. 2 are double-sided, including surface cleaning and texturing step 2, phosphorus diffusion step 3 and associated PSG removal step 4. In addition, silicon nitride deposition step 6 can be carried out either single-sided or double-sided, although a single-sided silicon nitride deposition is generally preferred with no back-side silicon nitride layer in the generic solar cell structure. The manufacturing flow of crystalline silicon solar cells needs to accommodate the double-sided process steps, especially the phosphorous furnace diffusion process. The aluminum (p-type) field deposition in backside metalization 9 compensates phosphorous (n-type) dopant on the wafer backside, and the edge isolation step 5 is critical to a functional solar cell by preventing shorts between n-type emitter at front and p-type collector at back of the substrates in the final structure.
The present invention also relates to preparation of thin semiconductor substrates. Substrates for use in the field of electronics, optoelectronics, and microelectromechanical systems (MEMS) devices are generally obtained by slicing/cutting/separating ingots. In the case of mono-crystalline silicon, for example, the ingots are obtained from a bath of molten silicon using the Czochralski (Cz) or the float zone (Fz) methods. These conventional methods produce cylindrical ingots which are cut by a circular or wire saw into slices perpendicular to the axis of the cylindrical ingot. The cut of the cylindrical ingots results in round wafers which are common for fabrication of general electronics and MEMS devices. In crystalline silicon solar cell production, silicon blocks are first prepared from the cylindrical ingots, before being cut into square or substantially square wafers.
Microprocessor and memory devices can function properly with less than one micron of silicon thickness. However, current silicon substrates in mass production are significantly thicker. 150 mm diameter silicon wafers have a standard thickness of ˜675 microns, 200 mm diameter silicon wafers have a standard thickness of ˜725 microns, and 300 mm diameter wafers have a standard thickness of ˜775 microns. A silicon-on-insulator (SOI) process has been developed to laminate a sub-micron pristine silicon layer on top of another insulating substrate (such as a silicon wafer with an insulating silicon oxide top layer). An improvement of transistor switching speed and a reduction in transistor power consumption have been reported for integrated circuits fabricated on the SOI substrate.
In production of general electronic devices with integrated circuits, multiple devices are first fabricated on a single wafer, and the devices at this stage are known as dies on the wafers. After completion of the manufacturing flow, wafers are cut along x- and y-directions to isolate individual dies, before each functional die is packaged with proper encapsulation and input/output (I/O) connectors. Often the wafers are thinned down from the back side before the wafer dicing step. The reduced substrate thickness can help to yield a lower profile in the final package. Thin dies can also be stacked up for additional functionalities or a more compact final packaging size, desirable in consumer electronics applications.
Wafer thinning is also adopted in fabrication of MEMS devices. MEMS devices such as micro-sensors and micro-actuators are usually manufactured on silicon wafers with process steps similar to fabrication of general electronic devices, with addition of mechanical components in dimensions of 1-100 microns. Silicon substrates of a thickness less than 100 microns are also flexible, suitable for some ultra light-weight, portable applications, e.g. new gadgets in curved or flexible forms.
With a solar cell structure design consisting of a surface texturing, an anti-reflective coating (ARC) layer deposition on the front surface and a reflector layer deposition at the back surface, solar cells of 18-24% efficiency are currently manufactured on mono-crystalline silicon substrates of >150 microns thickness. With some advanced light trapping technologies, it is conceivable to maintain the high solar cell efficiency with a silicon substrate of 100 microns or less in thickness.
In crystalline silicon solar cell production, ˜180 micron thick substrates (156 mm×156 mm or 125 mm×125 mm square) are common today, while ˜150 micron substrate thickness are becoming available with the advanced wire-saw systems to cut silicon ingots/blocks.
Silicon substrate cost often accounts for >50-60% of total manufacturing cost of mono-crystalline silicon solar cells. Thus there is a significant economical incentive to reduce silicon substrate thickness without reducing cell efficiency and without increasing manufacturing complexity/cost. However, current silicon substrate preparation technologies have their limitations. A cutting of hard materials such as silicon by wire saws is associated with considerable consumable cost (cutting wires and slurries) and a significant kerf loss, i.e. the amount of silicon removed by cutting wires. Despite of the continuous improvements in wiresaw equipment, process and materials, it remains challenging to produce wafers of less than 100 microns thickness with a kerf loss of less than 100 microns.
Alternative thin substrate technologies have been proposed for crystalline silicon solar cell production. In one method, ultrathin silicon wafers of less than 20 microns are produced by implantation of high energy hydrogen ions into silicon substrates, followed by a thermal or mechanical exfoliation. The idea is analogous to the commercial silicon-on-insulator (SOI) substrate technologies in advanced IC manufacturing. In another method, deposition of a thin metal (e.g. nickel) layer on the silicon substrate surface is followed by a low temperature anneal to form a thin metal silicide interface layer. A thin silicon wafer can then be exfoliated from the substrate by a mechanical wedge. Both silicon exfoliation methods can be repeated to produce multiple ultrathin silicon wafers (10-50 microns) from a single substrate with a negligible kerf loss.
Even though the silicon materials consumption can be lowered by the silicon exfoliation technologies, hurdles exist for their adoption in mass production of solar cells. A reliable handling of ultrathin substrates of <50 micron thickness can be difficult. Different from wiresaw cutting of a silicon ingot which can produce multiple wafers in parallel, silicon wafers can only be the substrate surface may also be necessary. As a result, manufacturing cost rises along with an increase of work-in-progress (WIP) inventory and cycle time. An adoption of the ultrathin silicon substrates can also require some significant exfoliated from a silicon substrate one at a time. A periodic reconditioning of modifications in solar cell manufacturing processes. An ultrathin substrate requires a more sufficient light trapping to maintain a high solar cell efficiency, yet a proper surface texturing for efficient light trapping is difficult on a Si(111) surface, the preferred surface orientation for the silicon wafer exfoliation technologies. In addition, alternative metalization technologies may need to be developed to accommodate the fragile ultrathin silicon substrates.
The methods used for substrate fabrication in the present invention can involve a laser irradiation process. Different lasers have different active media for coherent light generation. The most common active media include gases (in gas lasers), rare-earth element doped crystals (in solid state lasers), and semiconductor materials (in semiconductor lasers). Other laser types include chemical lasers, dye lasers, metal vapor lasers, etc.
In a gas laser, an electrical circuit is discharged through a gas to produce a coherent light. For example, CO2 lasers can emit hundreds of kilowatts at 10.6 microns, and are often used in industrial applications such as cutting and welding. Excimer lasers are a subgroup of gas lasers which are powered by a chemical reaction involving an excited dimer, or excimer. Common ultraviolet (UV) excimer lasers include F2 laser (emitting at 157 nm), ArF laser (193 nm), KrCl laser (222 nm), KrF laser (248 nm), XeCl laser (308 nm), and XeF laser (351 nm).
In solid state lasers, a crystalline or glass rod is “doped” with ions for the required energy states in coherent light generation. Yttrium aluminum garnet (Nd:YAG), yttrium lithium fluoride (Nd:YLF) and yttrium orthovanadate (Nd:YVO4) lasers can produce powerful pulses at 1064 nm. The laser intensity can be amplified through an optical fiber. The so called fiber lasers can deliver multi-kilowatt laser powers with an excellent electricity to laser power conversion efficiency, and have increasing industrial applications in cutting, welding and marking of metals and other materials. Common Diode Pumped Solid State (DPSS) lasers wavelength is 1064 nm, frequency-doubled 532 nm (green), frequency-tripled 355 nm (UV) and frequency-quadrupled 266 nm (UV).
Semiconductor lasers are commonly known as laser diodes. The active medium in laser diodes is a semiconductor material with a p-n junction. The emitting wavelength of laser iodides can range from ˜0.4 to 20 microns, with applications in telecommunications, holography, printing, and machining/welding. Laser iodides can also serve as pump sources for other lasers.
There are a number of laser applications in electronic device fabrications. The first group of applications is laser patterning/scribing. Laser patterning processes have been adopted in IC packaging and solar cell production, via a direct materials ablation process. A similar materials ablation process can also be used for laser dicing of wafers into individual dies. An alternative method for laser dicing involves focusing a high intensity laser beam inside the substrates. In the so-called Stealth Dicing process, the substrate materials is transparent to the laser irradiation of the basic frequency, but can be modified by a multi-photon absorption process at the laser converging point inside the substrate. After completion of the laser scan along the scribe lines, wafers are bonded to a supporting tape. When the supporting tape is stretched, dies can be separated with a near-zero kerf loss.
Some other laser-based processes involve a melt or sub-melt of substrate materials. Applications include dopant activation on silicon wafers in advanced transistor fabrications, and amorphous silicon film crystallization on glass substrates as backplanes for high-resolution flat panel displays. With a careful materials design and laser wavelength/power selection, a laser irradiation can also selectively melt a bonding layer and detach thin films/materials from the substrates. Applications include laser liftoff of LED dies from substrates (sapphire, silicon, etc.), and release of flexible displays from temporary carriers.
The present invention is also related to substrate handling in production of electronics devices. Substrates such as semiconductor wafers or large sheets of glass can be held in compliance to substrate chucks by an electrostatic force or a pressure delta between two sides of the substrates. Some substrate chucks are in a direct physical contact with the substrates. In other chuck designs, substrate chucks are in a close proximity to but not in a direct physical contact with the substrates. The non-contact substrate chucks often adopt a fluid-mechanical design and operate like a return spring. The working distance (between the substrates and the chuck) and stiffness of the chuck “spring” can be optimized. Substrates can also be transported across the surface of stationary non-contact chucks. In flat panel display panel production, non-contact fluid-mechanical chucks have been used for automation of glass substrates in coating, patterning, and optical inspection/metrology processes. In thin film solar production, non-contact fluid-mechanical chucks have been adopted in automation of substrates for laser scribing, etc.